In accordance with miniaturization of semiconductors, the density of a wiring pattern increases, and the width of trenches (grooves) of the pattern also becomes narrower. Technologies for filling the trench with an insulating film have been developed from the related art (for example, the technology disclosed in Patent Document 1 and the like).
The technology disclosed in Patent Document 1 is a technology aiming at manufacturing a semiconductor device which employs an STI separation method such that voids (gaps) do not remain and no damage is left on a silicon substrate even in a groove having an extremely narrow width and a high aspect ratio. In the technology, in the groove fainted on the silicon substrate, a Si-rich silicon oxide film (SiOXCY film, X<2) containing carbon is deposited to be thicker than a depth of the groove by a bias type high-density plasma chemical vapor deposition method (CVD), the Si-rich silicon oxide film is changed to a SiO2 film while eliminating the voids on the inside of the Si-rich silicon oxide film by performing heat treatment in an oxidizing atmosphere, and then, flattening is performed by a chemical mechanical polishing (CMP) method.